NV_BLKBOX_SINK error in vivado / FPGA implementation #303

Hi all,

I am getting the following error while trying to synthesize my design for implementing NVDLA on an FPGA. I am using the Zynq ultrascale+ family.

[Project 1-486] Could not resolve non-primitive black box cell 'design_1_design_1_wrapper_0_0_NV_BLKBOX_SINK_HD1725' instantiated as 'design_1_i/design_1_wrapper_0/inst/design_1_i/NV_nvdla_0/inst/u_partition_p/u_NV_NVDLA_sdp/u_rdma/u_nrdma/u_lat_fifo/ram/r_nv_ram_rwsp_16x65/UJ_BBOX2UNIT_UNUSED_pwrbus_31' ["/home/user/project_create16/project_create16.srcs/sources_1/bd/design_1/ip/design_1_design_1_wrapper_0_0/ipshared/ab69/src/nv_ram_rwsp_16x65_logic.v":132]

One solution I found was to define FPGA macro and set it to 1. I added that in the Defines found in the project settings in Vivado. Also, I added this macro in every possible source files I am using, as: `define FPGA 1 . I also made a separate .vh file and have added that as a Global include . But none of this seems to work and I still get the error. Also, I get the BLKBOX error only when I create the wrapper. If I don't create the wrapper and try to connect the combination of (NVDLA IP and NVDLA_apb2csb IP) with the Zynq ultra-scale+ block, the synthesis, and implementation passes.

So my question is, is it not required to create the wrapper? And if it is required, should I be doing anything else to get rid of this error? Any help and suggestions will be highly appreciated. Thank you!