Post by jarodz
Hi,
The following messages are displayed when I run simulation with modelsim
6.0.
(vsim-PLI-3691) ../TASK/jpegformat.v(72): Expected a system task, not a
system function '$fseek'.
From your title and the error message, it appears that you tried to use
$fseek as a task. It is a function, and returns a value. You must call
it as a function.
In other words, you tried to do something like
begin
$fseek(fd,0,0);
end
You must instead do something like
integer code;
begin
code = $fseek(fd,0,0);
end
Or actually use the return value as it was intended
begin
if ($fseek(fd,0,0) == -1)
$display("ERROR: fseek failed");
end
In C, you can use a function call as a statement and the return
value will just get thrown away. An expression is a legal
statement in C. This is not true in Verilog.
